1. Field of the Invention
The present invention is related to active radio freqency elements and techniques for packaging said elements so as to improve operation and reliability characteristics.
2. Description of the Prior Art
Many attempts have been made to develop radio frequency band amplifiers that are low in noise, rugged and immune to the environment. However, the design of most prior devices have apparently required certain trade offs to obtain devices suitable for particular uses.
U.S. Pat. Nos. 3,784,883, 3,908,185 and 3,958,195 are each directed to providing devices hermetically sealed in packages to protect them from the environment. However, each of the devices disclosed in the aforementioned patents incorporate sealing techniques which inherently introduce significant parasitic impedances into the operation of the devices at high frequencies.
For instance, U.S. Pat. No. 3,784,883 shows a transistor die mounted on an output microstrip line that is metalized onto a ceramic wafer. An input microstrip line is diametrically opposed to the output microstrip across a gap and is also metalized onto the ceramic wafer. A ceramic cap is mounted in contact with both the input and output microstrips so as to enclose the transistor die.
In U.S. Pat. No. 3,908,185, a semiconductor pellet is shown mounted on an isolated metalized island layer. A grounded metalized layer surrounds the island. The pellet is shown with its base wired to the grounded layer; the collector connected to the island; the island wired to an output lead; and the emitter wired to an input lead. An annular spacer of Al.sub.2 O.sub.3 surrounds the semiconductor pellet and is located on the grounded layer. The upper surface of this spacer contains input and output lead extension layers to which the aforementioned collector and emitter wires are connected. A high temperature glass sealing ring provides the sealant between the upper surface of the spacer and a ring to support a stainless steel cap.
In U.S. Pat. No. 3,958,195 a transistor package is shown which includes a generally planar ground plane metalization surrounding a transistor mounting pad supporting a transistor die. An electrically insulative aperture spacer plate is disposed over the ground plane structure with the aperture of the spacer in registration over the transistor. The input and output lead structures are disposed overlaying the aperture spacer so that the input and output lead structures extend across the spacer and intersect with the aperture. The common lead structure extends across the spacer adjacent the aperture, as does the input and output leads. Interconnect leads interconnect the leads overlaying the spacer with the underlying ground plane and transistor electrodes through the aperture in the spacer. A ceramic cap is sealed over the aperture and is in contact with the common, input and output leads.